• Korpelainen, Virpi
• Ylilammi, Markku
• Gao, Feng
• Puurunen, Riikka L.
• Utriainen, Mikko

Abstract

The downscaling of future semiconductor devices with increasing 3D character leads to increasing demand of highly conformal thin films. Similarly, conformal deposition enables new opportunities in microelectromechanical systems (MEMS), photonics, and other material science applications. Although, conformality is a core value proposition of Atomic Layer Deposition (ALD) and related thin film processing methods, it is challenging to measure and quantify, while standardized measurement methods do not exist.A potential approach to circumvent the challenge is a MEMS-based all-silicon lateral high aspect ratio (LHAR) test structure, PillarHall® developed at VTT 1-3. The test chip is compatible for CMOS process lines and suitable for wide temperature range. PillarHall® Prototype 3B LHAR test structure consists of a lateral gap of typically 500 nm (optionally, 100 to 2000 nm) in height under a polysilicon silicon membrane, supported by silicon pillars. One test chip consists of multiple LHAR structures, where the gap length varies from 1 to 5000 µm, giving aspect ratios (length vs height) for the typical ~500 nm gap of 2:1 to 10 000:1. Silicon pillars provide dimensional accuracy by stabilizing membrane roof. The pillars and additional distance indicator lines provide internal length scale for visual examination. PillarHall® Test Chips are available at VTT for applications and research cooperation. The test chips have been employed with good success in ALD, conformality metrology for baseline and figure-of-merits as well as comparative studies with vertical AR structures. Future opportunities are e.g in process optimization and control & monitoring.

Topics

• impedance spectroscopy
• thin film
• semiconductor
• Silicon
• atomic layer deposition