| People | Locations | Statistics |
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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Kononenko, Denys |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Li, Xu
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (10/10 displayed)
- 2020Temperature evolution of the magnetic properties of Ag/Fe nanodot arrayscitations
- 2020Polarity dependence in Cl2-based plasma etching of GaN, AlGaN and AlNcitations
- 2020Optimization of ohmic contact for AlGaN/ GaN HEMT on low resistivity siliconcitations
- 2020Polarity dependence in Cl 2 -based plasma etching of GaN, AlGaN and AlNcitations
- 2020Optimization of ohmic contact for AlGaN/GaN HEMT on low-resistivity siliconcitations
- 2017Damage to Algan/Gan Power Device Materials from Cl2 and Ar Plasma Based Atomic Layer Etching and its Elimilation via a Low Temperature Rapid Thermal Annealing
- 2012Direct Nano-Patterning of Commercially Pure Titanium with Ultra-Nanocrystalline Diamond Stamps
- 2012Direct nanopatterning of commercially pure titanium with ultra-nanocrystalline diamond stampscitations
- 2009III-V MOSFET Fabrication and Device (Fabrication process of e.g. group III-V MOSFET for nano complementary metal oxide semiconductor application, involves heat treating metal contact structure to produce alloy region within semiconductor substrate)
- 2008Ino.75Gao.25As channel III–V MOSFETs with leading performance metrics
Places of action
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patent
III-V MOSFET Fabrication and Device (Fabrication process of e.g. group III-V MOSFET for nano complementary metal oxide semiconductor application, involves heat treating metal contact structure to produce alloy region within semiconductor substrate)
Abstract
A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45.degree. to 90.degree.. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.