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Naji, M. |
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Motta, Antonella |
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Aletan, Dirar |
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Mohamed, Tarek |
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Ertürk, Emre |
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Taccardi, Nicola |
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Kononenko, Denys |
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Petrov, R. H. | Madrid |
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Alshaaer, Mazen | Brussels |
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Bih, L. |
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Casati, R. |
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Muller, Hermance |
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Kočí, Jan | Prague |
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Šuljagić, Marija |
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Kalteremidou, Kalliopi-Artemi | Brussels |
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Azam, Siraj |
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Ospanova, Alyiya |
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Blanpain, Bart |
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Ali, M. A. |
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Popa, V. |
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Rančić, M. |
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Ollier, Nadège |
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Azevedo, Nuno Monteiro |
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Landes, Michael |
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Rignanese, Gian-Marco |
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Conway, P. P.
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (6/6 displayed)
- 2008Integrated optical and electronic interconnect printed circuit board manufacturing
- 2006Grain features of SnAgCu solder and their effect on mechanical behaviour of micro-jointscitations
- 2002Electroless nickel bumping of aluminum bondpads - Part II: Electroless nickel platingcitations
- 2000Solder paste reflow modeling for flip chip assembly
- 2000Investigation of a solder bumping technique for flip-chip interconnection
- 2000Under bump metallisation of fine pitch flip-chip using electroless nickel depositioncitations
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article
Investigation of a solder bumping technique for flip-chip interconnection
Abstract
As the demand for flip-chip products increases, the need for low cost high volume manufacturing processes also increases. Currently solder paste printing is the wafer bumping method of choice for device pitches down to 150-200 mu m. However, limitations in print quality and stencil manufacture mean that this technology is not likely to move significantly below this pitch and new methods will be required to meet the demands predicted by the technology roadmaps. This paper describes experiments conducted on carriers made from silicon for bumping of die using solder paste. An anisotropic etching process was used to generate pockets in the silicon surface into which solder paste was printed. Die were then placed against the carrier and reflowed to transfer the solder directly to the bondpads. An assessment was carried out of the potential application and limitations of this technique for device pitches at 225 and 127 mu m.