| People | Locations | Statistics |
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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Kononenko, Denys |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Wallace, Andrew
Heriot-Watt University
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (4/4 displayed)
- 2021The influence of load on dry and tribocorrosive sliding of AISI 4330 and 15-5PH against cast ironcitations
- 2020Fast Surface Detection Using Single-Photon Detection Eventscitations
- 2015RIPL: An Efficient Image Processing DSL for FPGAs
- 2014Inhibition by poly(acrylic acid) and morphological changes in calcium carbonate and calcium carbonate/calcium sulfate crystallization on silica fiberscitations
Places of action
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document
RIPL: An Efficient Image Processing DSL for FPGAs
Abstract
Field programmable gate arrays (FPGAs) can accelerate image processing by<br/>exploiting fine-grained parallelism opportunities in image operations. FPGA<br/>language designs are often subsets or extensions of existing languages, though<br/>these typically lack suitable hardware computation models so compiling them to<br/>FPGAs leads to inefficient designs. Moreover, these languages lack image<br/>processing domain specificity. Our solution is RIPL, an image processing domain<br/>specific language (DSL) for FPGAs. It has algorithmic skeletons to express<br/>image processing, and these are exploited to generate deep pipelines of highly<br/>concurrent and memory-efficient image processing components.