Materials Map

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The Materials Map is an open tool for improving networking and interdisciplinary exchange within materials research. It enables cross-database search for cooperation and network partners and discovering of the research landscape.

The dashboard provides detailed information about the selected scientist, e.g. publications. The dashboard can be filtered and shows the relationship to co-authors in different diagrams. In addition, a link is provided to find contact information.

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The Materials Map is still under development. In its current state, it is only based on one single data source and, thus, incomplete and contains duplicates. We are working on incorporating new open data sources like ORCID to improve the quality and the timeliness of our data. We will update Materials Map as soon as possible and kindly ask for your patience.

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Topics

Publications (1/1 displayed)

  • 2019Electrical Properties of Monocrystalline Thin Film Si for Solar Cells Fabricated By Rapid Vapor Deposition with Nano-Surface Controlling Double Layer Porous Si in H2citations

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Hasegawa, Kei
1 / 1 shared
Shibahara, Ryotaro
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Fourmond, Erwann
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Ihara, Manabu
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2019

Co-Authors (by relevance)

  • Hasegawa, Kei
  • Shibahara, Ryotaro
  • Fourmond, Erwann
  • Ihara, Manabu
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document

Electrical Properties of Monocrystalline Thin Film Si for Solar Cells Fabricated By Rapid Vapor Deposition with Nano-Surface Controlling Double Layer Porous Si in H2

  • Hasegawa, Kei
  • Shibahara, Ryotaro
  • Fourmond, Erwann
  • Ihara, Manabu
  • Noda, Suguru
Abstract

Introduction To reduce the Si thickness with maintaining the high quality is a promising approach to reduce the cost of monocrystalline Si solar cell. A major method to fabricate monocrystalline thin Si is epitaxy by Chemical Vapor Deposition (CVD) and Layer Transfer Process (LTP) as shown in Fig. 1. A seed layer and a sacrificial layer such as double layer porous Si (DLPS) which consist of a Low Porous Layer (LPL) and a High Porous Layer (HPL) are fabricated on the surface of a monocrystalline Si wafer, and then Si is epitaxially deposited on the seed layer. This wafer can then be reused in LTP, thus further reducing the material cost of these Si cells. There remain two challenging issues: (ⅰ) crystal defect introduced during epitaxy caused by the roughness of the seed layer 1) and (ⅱ) low deposition rate and yield of epitaxy by CVD. To solve problem (ⅰ), we proposed a Zone Heating Recrystallization (ZHR) method 2) to smoothen the DLPS surface as shown in Fig.2. The structure of the DLPS surface can be modified by using an upper lamp heater to scan the surface in one direction and a bottom heater to pre-heat Si substrate. To solve problem (ⅱ), we proposed a Rapid Vapor Deposition (RVD) method 3) as shown in Fig.3. By depositing Si under a high vapor pressure by heating the source Si to over 2000℃, the deposition rate of over 10 μm/min with a higher yield is achieved. By applying both the ZHR and RVD methods, we successfully reduced the roughness of a DLPS surface and obtained monocrystalline Si with Si wafer level. The critical effect of lowering the roughness of a DLPS surface to R ms < 0.3 nm was

Topics
  • porous
  • impedance spectroscopy
  • surface
  • thin film
  • mass spectrometry
  • defect
  • recrystallization
  • chemical vapor deposition