| People | Locations | Statistics |
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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Kononenko, Denys |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Todri-Sanial, Aida
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (14/14 displayed)
- 2023Non-volatile resistive switching mechanism in single-layer MoS2 memristorscitations
- 2023Non-volatile resistive switching mechanism in single-layer MoS2 memristors:insights from ab initio modelling of Au and MoS2 interfacescitations
- 2023Roadmap for Unconventional Computing with Nanotechnology
- 2022First-Principles Simulations of Vacancies and Grain Boundaries in Monolayer MoS2-Au Interfaces for Unconventional Computing Paradigm
- 2020Stretchable Strain Sensors for Human Movement Monitoringcitations
- 2019Investigation of Pt-Salt-Doped-Standalone-Multiwall Carbon Nanotubes for On-Chip Interconnect Applicationscitations
- 2019Investigation of Pt-Salt-Doped-Standalone- Multiwall Carbon Nanotubes for On-Chip Interconnect Applicationscitations
- 2019Microelectronics Department Half-Day Seminar
- 2018Atomistic- to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnectscitations
- 2017Design methodology for 3D power delivery networks
- 2015Design Methodology for 3D Power Delivery Networks
- 2014Globally Constrained Locally Optimized 3-D Power Delivery Networkscitations
- 2014Design Space Exploration Of Emerging Technologies For Energy Efficiency
- 2014Habilitation - Design Space Exploration Of Emerging Technologies For Energy Efficiency
Places of action
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thesis
Habilitation - Design Space Exploration Of Emerging Technologies For Energy Efficiency
Abstract
As the demand for denser and faster electronics is growing, semiconductor industry has responded by aggressively scaling transistor sizes to several nanometers. Nano-scale devices provide higher density circuits while imposing crucial power, thermal and reliability problems to the system. As wire width continue to shrink, copper interconnects in high-performance systems will suffer from significant increase in resistivity due to surface roughness and grain boundary scattering resulting in electromigration issues. Furthermore, as technology scaling following Moore’s law is reaching its limits, 3D integration is a novel, promising and fast-emerging technology. 3D integration provides several advantages over 2D ICs by enabling, higher functionality, small form factor and heterogeneous implementation. The work presented in the HDR manuscript addresses the challenges of designing reliable and energy efficient circuits and systems for emerging technologies. It covers: -modeling and simulation for understanding the physical, electrical and thermal behavior on 3D integrated circuits. -physical design methods for power and signal integrity of 3D integrated circuits. -energy efficiency exploration on circuits based on carbon nanotube (CNT) interconnects.