| People | Locations | Statistics |
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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Kononenko, Denys |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Pichon, Laurent
Institut d'Électronique et des Technologies du numéRique
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (8/8 displayed)
- 2022Comparative study on quantitative carbon content mapping in archaeological ferrous metals with laserinduced plasma spectroscopy (LIBS) and nuclear reaction analysis (NRA) for 3D representation by LIBScitations
- 2021In-depth analysis of electrical characteristics for polycrystalline silicon vertical thin film transistorscitations
- 2019Industrial production of white earthenware in the Johnston-Vieillard manufactory (19th century): recipes evolution and production strategies
- 2009Fabrication of polycrystalline silicon nanowires using conventional UV lithography
- 2009Improvement in the determination by 1/f noise measurements of the interface state distribution in polysilicon TFTs in relation with the compensation law of Meyer Neldelcitations
- 2008Low frequency Noise in Polysilicon Thin Film Transistors: Effect of the Laser Annealing of the Active Layer
- 2004Compatibility of p-metal oxide semiconductor technology with the epitaxial YBa2CU3O7-delta growth on Si
- 2001Thin film transistors fabricated by in-situ doped unhydrogenated polysilicon films obtained by solid phase crystallization
Places of action
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document
Fabrication of polycrystalline silicon nanowires using conventional UV lithography
Abstract
Silicon nanowires are processed by using the sidewall spacer formation technique. This technique uses craftily a drawback of anisotropic etching to go beyond optical limits with conventional UV lithography for precision patterns. The final width of the spacer is controlled by the steepness of the etching side and by the uniformity of the wall recovering layer. In our process, a polysilicon layer is deposited by low pressure chemical vapour deposition technique on SiO2 wall network patterned by conventional UV lithography technique. Accurate control of the etching rate of the polysilicon leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. Networks of such parallel polysilicon nanowires were electrically tested in function of temperature (530K300K) with thermal activation EA ~ 0.3 eV