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Naji, M. |
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Motta, Antonella |
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Aletan, Dirar |
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Mohamed, Tarek |
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Ertürk, Emre |
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Taccardi, Nicola |
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Kononenko, Denys |
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Petrov, R. H. | Madrid |
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Alshaaer, Mazen | Brussels |
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Bih, L. |
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Casati, R. |
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Muller, Hermance |
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Kočí, Jan | Prague |
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Šuljagić, Marija |
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Kalteremidou, Kalliopi-Artemi | Brussels |
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Azam, Siraj |
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Ospanova, Alyiya |
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Blanpain, Bart |
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Ali, M. A. |
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Popa, V. |
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Rančić, M. |
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Ollier, Nadège |
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Azevedo, Nuno Monteiro |
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Landes, Michael |
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Rignanese, Gian-Marco |
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Vandermeulen, Jasper
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (4/4 displayed)
- 2018Comparison between collective coordinate models for domain wall motion in PMA nanostrips in the presence of the Dzyaloshinskii-Moriya interactioncitations
- 2015A collective coordinate approach to describe magnetic domain wall dynamics applied to nanowires with high perpendicular anisotropycitations
- 2015Transverse domain wall based logic and memory concepts for all-magnetic computing
- 2015Logic and memory concepts for all-magnetic computing based on transverse domain wallscitations
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document
Transverse domain wall based logic and memory concepts for all-magnetic computing
Abstract
We introduce a non-volatile digital logic and memory concept in which the binary data is stored in the transverse magnetic domain walls rather than the magnetic domains present in in-plane magnetized nanowires with sufficiently small cross sectional dimensions. We assign the digital bit to the two possible orientations of the transverse domain wall. Numerical proofs-of-concept designs are presented for a NOT-, AND- and OR-gate, a FAN-out as well as a reading and writing device. For some concepts, the functionality is achieved over a wide range of variable design parameters, numerically demonstrating robustness. Contrary to the chirality based vortex domain wall logic gates introduced in Phys. Rev. Appl. 2 (2014), the presented concepts remain applicable when miniaturized.Moreover, they are electrical current driven, making the technology compatible with the racetrack memory concept. The individual devices can be easily combined to form logic networks with clock speeds that scale linearly with decreasing design dimensions, starting from envisaged clock speeds of about 66 MHz for the sub-optimal designs presented. This opens opportunities to an all-magnetic computing technology where the digital data is stored and processed under the same magnetic representation.