People | Locations | Statistics |
---|---|---|
Naji, M. |
| |
Motta, Antonella |
| |
Aletan, Dirar |
| |
Mohamed, Tarek |
| |
Ertürk, Emre |
| |
Taccardi, Nicola |
| |
Kononenko, Denys |
| |
Petrov, R. H. | Madrid |
|
Alshaaer, Mazen | Brussels |
|
Bih, L. |
| |
Casati, R. |
| |
Muller, Hermance |
| |
Kočí, Jan | Prague |
|
Šuljagić, Marija |
| |
Kalteremidou, Kalliopi-Artemi | Brussels |
|
Azam, Siraj |
| |
Ospanova, Alyiya |
| |
Blanpain, Bart |
| |
Ali, M. A. |
| |
Popa, V. |
| |
Rančić, M. |
| |
Ollier, Nadège |
| |
Azevedo, Nuno Monteiro |
| |
Landes, Michael |
| |
Rignanese, Gian-Marco |
|
Nowakowski, Pawel
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (9/9 displayed)
- 2022Large Field of View and Artifact-Free Plan View TEM Specimen Preparation by Post-FIB Ar Milling
- 2022An Innovative Technique for Large-Scale Delayering of Semiconductor Devices with Nanometric-Scale Surface Flatness
- 2020Cutting-Edge Sample Preparation from FIB to Ar Concentrated Ion Beam Milling of Advanced Semiconductor Devices
- 2019Ultra-Thinning of Silicon for Backside Fault Isolationcitations
- 2019High Throughput and Multiple Length Scale Sample Preparation for Characterization and Failure Analysis of Advanced Semiconductor Devices
- 2018Narrow-Beam Argon Ion Milling of Ex Situ Lift-Out FIB Specimens Mounted on Various Carbon-Supported Gridscitations
- 2017Advanced Tools and Techniques for Delayering and Cross-Sectioning Semiconductor Devicescitations
- 2011Recent Developments in the Study of Grain Boundary Segregation by Wavelength Dispersive X-Ray Spectroscopy (WDS)
- 2010RuO<sub>2</sub> thin films deposited by spin coating on silicon substrates: pH‐dependence of the microstructure and catalytic propertiescitations
Places of action
Organizations | Location | People |
---|
article
Ultra-Thinning of Silicon for Backside Fault Isolation
Abstract
<jats:title>Abstract</jats:title><jats:p>The size of devices on state-of-the-art integrated circuits continues to decrease with each technology node, which drives the need to continually improve the resolution of electrical failure analysis techniques. Solid immersion lenses are commonly used in combination with infrared light to perform analysis from the backside of the device, but typically only have resolutions down to ~200 nm. Improving resolution beyond this requires the use of shorter wavelengths, which in turn requires a silicon thickness in the 2 to 5 µm range. Current ultra-thinning techniques allow consistent thinning to ~10 µm. Thinning beyond this, however, has proven challenging. In this work, we show how broad beam Ar ion milling can be used to locally thin a device’s backside silicon until the remaining silicon thickness is &lt; 5 µm.</jats:p>