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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Phung, Luong Viêt
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (7/7 displayed)
- 2024Electrical characteristics and trap signatures for Schottky barrier diodes on 4H-SiC, GaN-on-GaN, AlGaN/GaN epitaxial substratescitations
- 2023Full-SiC Single-Chip Buck and Boost MOSFET-JBS Converters for Ultimate Efficient Power Vertical Integration
- 2023Vertical pin diodes on large freestanding (100) diamond film
- 2022Design of a test package for high voltage SiC diodes
- 2016Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applicationscitations
- 2013Edge Termination Design Improvements for 10 kV 4H-SiC Bipolar Diodescitations
- 2012Edge termination design improvements for 10 kV 4H-SiC bipolar diodes
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conferencepaper
Full-SiC Single-Chip Buck and Boost MOSFET-JBS Converters for Ultimate Efficient Power Vertical Integration
Abstract
This paper aims at demonstrating the relevance of a new design perimeter for power switching cells through a monolithic vertical integration approach on a multi-terminal power chip with Wide-Band Gap material such as 4H silicon carbide (SiC). Multi-terminal monolithic architectures making use quasi-only of vertical unipolar switch (VDMOS) and JBS diode architecture within the context of a 600V/10A full integration of switching cells on 4H-SiC chips are proposed and validated through Sentaurus 2D numerical simulations. The key method to etch and to fill the metallic via needed to connect the VDMOS and the JBS from top to back side of the SiC wafer is presented. The first optimization of the electroplating process resulted in a Ni metal layer of about 5µm thick.