• Spirito, Davide
• Tillack, Bernd
• Mai, Andreas
• Schubert, Markus Andreas
• Corley-Wiciak, Agnieszka Anna
• Klesse, Wolfgang Matthias
• Yamamoto, Yuji
• Corley-Wiciak, Cedric
• Anand, Ketan

Abstract

<jats:p>Dislocation free local SiGe-on-insulator virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around ~1.25 µm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO<jats:sub>2</jats:sub> / Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO<jats:sub>2</jats:sub> cap, is obtained. Uniform Ge content of ~40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ~0.65% is found which could be due to thermal expansion difference between SiO<jats:sub>2</jats:sub> and Si. In the SiGe, tensile strain of ~1.4% along &lt;010&gt; direction, which is higher compared to that along &lt;110&gt; direction, is observed. The tensile strain is induced from both [110] and [-110] directions. Threading dislocations in the SiGe are located only ~400 nm from Si pillar and stacking faults are running towards &lt;110&gt; directions, resulting in wide dislocation-free area formation in SiGe along &lt;010&gt; due to horizontal aspect ratio trapping.</jats:p>

Topics

• impedance spectroscopy
• surface
• phase
• dislocation
• thermal expansion
• etching
• chemical vapor deposition
• stacking fault