| People | Locations | Statistics |
|---|---|---|
| Naji, M. |
| |
| Motta, Antonella |
| |
| Aletan, Dirar |
| |
| Mohamed, Tarek |
| |
| Ertürk, Emre |
| |
| Taccardi, Nicola |
| |
| Kononenko, Denys |
| |
| Petrov, R. H. | Madrid |
|
| Alshaaer, Mazen | Brussels |
|
| Bih, L. |
| |
| Casati, R. |
| |
| Muller, Hermance |
| |
| Kočí, Jan | Prague |
|
| Šuljagić, Marija |
| |
| Kalteremidou, Kalliopi-Artemi | Brussels |
|
| Azam, Siraj |
| |
| Ospanova, Alyiya |
| |
| Blanpain, Bart |
| |
| Ali, M. A. |
| |
| Popa, V. |
| |
| Rančić, M. |
| |
| Ollier, Nadège |
| |
| Azevedo, Nuno Monteiro |
| |
| Landes, Michael |
| |
| Rignanese, Gian-Marco |
|
Todri-Sanial, Aida
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (14/14 displayed)
- 2023Non-volatile resistive switching mechanism in single-layer MoS2 memristorscitations
- 2023Non-volatile resistive switching mechanism in single-layer MoS2 memristors:insights from ab initio modelling of Au and MoS2 interfacescitations
- 2023Roadmap for Unconventional Computing with Nanotechnology
- 2022First-Principles Simulations of Vacancies and Grain Boundaries in Monolayer MoS2-Au Interfaces for Unconventional Computing Paradigm
- 2020Stretchable Strain Sensors for Human Movement Monitoringcitations
- 2019Investigation of Pt-Salt-Doped-Standalone-Multiwall Carbon Nanotubes for On-Chip Interconnect Applicationscitations
- 2019Investigation of Pt-Salt-Doped-Standalone- Multiwall Carbon Nanotubes for On-Chip Interconnect Applicationscitations
- 2019Microelectronics Department Half-Day Seminar
- 2018Atomistic- to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnectscitations
- 2017Design methodology for 3D power delivery networks
- 2015Design Methodology for 3D Power Delivery Networks
- 2014Globally Constrained Locally Optimized 3-D Power Delivery Networkscitations
- 2014Design Space Exploration Of Emerging Technologies For Energy Efficiency
- 2014Habilitation - Design Space Exploration Of Emerging Technologies For Energy Efficiency
Places of action
| Organizations | Location | People |
|---|
article
Atomistic- to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects
Abstract
In this paper, we present a hierarchical model for doped single-walled carbon nanotube (SWCNT) for on-chip interconnect application. Our model aims to study CVD grown SWCNTs while considering defects and contacts to metal electrodes. Both defects and poor contacts can worsen CNT conductivities and ultimately deteriorate their interconnect performance. We investigate the fundamental physical mechanism of charge-based doping with the purpose of improving SWCNT electrical conductivity as well as a potential solution to alleviating the impact of defects and contact resistances. We present an atomistic model to study the number of conducting channels of doped SWCNT with different vacancy defect configurations. Circuit-level electrical modeling and simulations are performed on SWCNT interconnect while considering the impact of doping, defects, and contact resistance. Simulation results show up to 80% resistance reduction by doping, where 17% of delay increases due to defects. Additionally, we observe doping can mitigate the impact of defects by more than 12%, but there is almost no improvement in the contact resistance.