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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Kononenko, Denys |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Kreupl, Franz
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (21/21 displayed)
- 2020Patterning Platinum by Selective Wet Etching of Sacrificial Pt-A1 Alloycitations
- 2019Graphenic carbon as etching mask: patterning with laser lithography and KOH etching
- 2019Highly Reliable Contacts to Silicon Enabled by Low Temperature Sputtered Graphenic Carbon
- 2018Carbon Wonderland from an Engineering Perspective
- 2017Graphenic Carbon: A Novel Material to Improve the Reliability of Metal-Silicon Contactscitations
- 2016Graphenic Carbon-Silicon Contacts for Reliability Improvement of Metal-Silicon Junctions
- 2016Graphenic carbon-silicon contacts for reliability improvement of metal-silicon junctionscitations
- 2015Trap passivation in memory cell with metal oxide switching element
- 2013TRAP PASSIVATION IN MEMORY CELL WITH METAL OXIDE SWITCHING ELEMENT
- 2013Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications—Part I: Process Developmentcitations
- 2012Integrated circuit including doped semiconductor line having conductive cladding
- 2011Integrated circuit including doped semiconductor line having conductive cladding
- 2010INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING
- 2009Integrated circuit including doped semiconductor line having conductive cladding
- 2007Silicon to nickel‐silicide axial nanowire heterostructures for high performance electronicscitations
- 2004High-current nanotube transistorscitations
- 2004Catalytic CVD of SWCNTs at Low Temperatures and SWCNT Devices
- 2004Chemical Vapor Deposition Growth of Single-Walled Carbon Nanotubes at 600 °C and a Simple Growth Modelcitations
- 2003Contact improvement of carbon nanotubes via electroless nickel depositioncitations
- 2001Method for fabricating an integrated circuit having at least one metallization plane
- 2001Template grown multiwall carbon nanotubes
Places of action
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article
Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications—Part I: Process Development
Abstract
Although horizontally-aligned carbon nanotube (HACNT) interconnects are the most common scenarios that have been modeled and analyzed in theoretical research, fabrication of HACNT test structures has remained an enigma until now. Through addressing several fabrication challenges, this paper reports a novel process that enables fabrication of high-density, long (over hundred microns), and thick (up to micrometer) HACNT interconnects. Furthermore, horizontal CNT-based 2-D Manhattan structure is demonstrated by properly designing the catalyst and flattening process. These structures are crucial for building angled interconnects and on-chip passive devices. In addition, to address the contact issue between metal and thick HACNT bundles, a multistep lithography combined with specifically designed metal deposition technique is performed to ensure full contact configuration. Using such a process, test structures with arrays of various sizes of HACNT bundle interconnects are fabricated. The process developed in this paper provides an important platform for future research and technology development of CNT-based interconnects and passive elements.