| People | Locations | Statistics |
|---|---|---|
| Naji, M. |
| |
| Motta, Antonella |
| |
| Aletan, Dirar |
| |
| Mohamed, Tarek |
| |
| Ertürk, Emre |
| |
| Taccardi, Nicola |
| |
| Kononenko, Denys |
| |
| Petrov, R. H. | Madrid |
|
| Alshaaer, Mazen | Brussels |
|
| Bih, L. |
| |
| Casati, R. |
| |
| Muller, Hermance |
| |
| Kočí, Jan | Prague |
|
| Šuljagić, Marija |
| |
| Kalteremidou, Kalliopi-Artemi | Brussels |
|
| Azam, Siraj |
| |
| Ospanova, Alyiya |
| |
| Blanpain, Bart |
| |
| Ali, M. A. |
| |
| Popa, V. |
| |
| Rančić, M. |
| |
| Ollier, Nadège |
| |
| Azevedo, Nuno Monteiro |
| |
| Landes, Michael |
| |
| Rignanese, Gian-Marco |
|
Andriulli, Francesco
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (3/3 displayed)
- 2020A Regularized Electric Flux Volume Integral Equation for Brain Imagingcitations
- 2017A Scaling-Less Newton-Raphson Pipelined Implementation for a Fixed-Point Reciprocal Operatorcitations
- 2017A scaling-less Newton-Raphson pipelined implementation for a fixed-point inverse square root operatorcitations
Places of action
| Organizations | Location | People |
|---|
article
A Scaling-Less Newton-Raphson Pipelined Implementation for a Fixed-Point Reciprocal Operator
Abstract
The reciprocal is a widespread operation in digital signal processing architectures. A usual method consists in using the Newton-Raphson algorithm or its derivatives, either in floating or in fixed-point formats. With the former format, the standardized format of the mantissa makes the implementation easier, but for the fixed-point format there are many possibilities. This forces a design with scaling of the input in order to respect a predetermined work range. Having the input in a known range makes it possible to compute a first approximation with coefficients stored in memory blocks. With this method, it is hard to propose a "ready to use" IP for all the fixed-point formats. In this letter, a novel architecture, which does not require scaling, is proposed. This design is totally pipelined, ROM-less and can be directly used in any architecture. The implementation was optimized to reach a maximum clock frequency of 740 MHz on a Virtex-7 Field-Programmable Gate Array (FPGA).