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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Kononenko, Denys |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Coinon, Christophe
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (9/9 displayed)
- 2022GAP(111)B-SE Surface for TMD epitaxial growth
- 2022In-plane InGaAs/Ga(As)Sb nanowire based tunnel junctions grown by selective area molecular beam epitaxycitations
- 2022Colloidal II–VI—Epitaxial III–V heterostructure: A strategy to expand InGaAs spectral responsecitations
- 2021Pushing the limit of lithography for patterning two-dimensional lattices in III-V semiconductor quantum wellscitations
- 2020Engineering a Robust Flat Band in III–V Semiconductor Heterostructurescitations
- 2019InAlAs/InGaAs-MSM photodetectors based on optical cavity using metallic mirrors: THz frequency operation, high quantum efficiency and high saturation currentcitations
- 2018Chemical nature of the anion antisite in dilute phosphide GaAs1−xPx alloy grown at low temperaturecitations
- 2017V-shaped InAs/Al<sub>0.5</sub>Ga<sub>0.5</sub>Sb vertical tunnel FET on GaAs (001) substrate with I<sub>ON</sub>=433 µA.µm<sup>-1</sup> at V<sub>DS</sub>= 0.5Vcitations
- 2017V-shaped InAs/Al 0.5 Ga 0.5 Sb vertical tunnel FET on GaAs (001) substrate with I ON =433 µA.µm -1 at V DS = 0.5Vcitations
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article
V-shaped InAs/Al<sub>0.5</sub>Ga<sub>0.5</sub>Sb vertical tunnel FET on GaAs (001) substrate with I<sub>ON</sub>=433 µA.µm<sup>-1</sup> at V<sub>DS</sub>= 0.5V
Abstract
We report on the fabrication of a near broken InAs/Al<sub>0.5</sub>Ga<sub>0.5</sub>Sb vertical TFET. The epitaxial structure is grown on a GaAs (001) substrate thanks to large mismatch accommodation at the GaSb/GaAs interface. The fabrication process involves an anisotropic and selective wet chemical etching of the InAs channel to form a V-shaped mesa with lateral side gates. This new architecture provides a large ON-current at room temperature while enabling an efficient pinch-off thanks to a reduced body thickness near the tunneling interface. With low temperature measurements, we identify the different mechanisms limiting the subthreshold slope at room temperature. At 77K, where the impact of defects is reduced, a minimum subthreshold slope of 71 mV/decade is achieved for VDS=0.1V with an I<sub>ON</sub>/I<sub>OFF</sub> current ratio larger than 6 decades demonstrating that a good trade-off between ON current and switching efficiency could be obtained with a near broken gap heterostructure based n-TFET.