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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Petrov, R. H. | Madrid |
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| Bih, L. |
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| Casati, R. |
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| Kočí, Jan | Prague |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Ali, M. A. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Potter, Richard
University of Liverpool
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (5/5 displayed)
- 2021Demonstration of a Fast, Low-Voltage, III-V Semiconductor, Non-Volatile Memorycitations
- 2020Band line-up investigation of atomic layer deposited TiAlO and GaAlO on GaNcitations
- 2017Atomic Layer Deposition of a Silver Nanolayer on Advanced Titanium Orthopedic Implants Inhibits Bacterial Colonization and Supports Vascularized de Novo Bone Ingrowthcitations
- 2016Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)<i>x</i>(Al2O3)1−<i>x</i> as potential gate dielectrics for GaN/AlxGa1−xN/GaN high electron mobility transistorscitations
- 2016Self-limiting atomic layer deposition of conformal nanostructured silver filmscitations
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document
Demonstration of a Fast, Low-Voltage, III-V Semiconductor, Non-Volatile Memory
Abstract
ULTRARAM™ is a III-V semiconductor memory technology which exploits resonant tunneling to allow ultra-low-energy memory logic switching (per unit area), whilst retaining non-volatility. Single-cell memories developed on GaAs substrates with a revised design and atomic-layer-deposition Al 2 O 3 gate dielectric demonstrate significant improvements compared to prior prototypes. Floating-gate (FG) memories with 20-μm gate length show 0/1 state contrast from 2.5-V program-read-erase-read (P/E) cycles with 500-μs pulse duration, which would scale to sub-ns switching speed at 20-nm node. Nonvolatility is confirmed by memory retention tests of 4×10 3 s with both 0 and 1 states completely invariant. Single cells demonstrate promising endurance results, undergoing 10 4 cycles without degradation. P/E cycling and disturbance tests are performed using half-voltages (±1.25 V), validating the high-density random access memory (RAM) architecture proposed previously. Finally, memory logic is retained after an equivalent of >10 5 P/E disturbances.