• Najmzadeh, M.
• Zeng, Y.
• Hu, C.
• Duarte, J. P.

Abstract

<p>In this paper, 2D MOSFET operation of a fully-depleted double-gate bulk MoS₂ is studied at a quasi-flatband of the back-gate for the first time. Several key device parameters such as equivalent oxide thickness (EOT), carrier concentration, flatband voltage, dielectric constant and carrier mobility were extracted from I-V and C-V characteristics and at room temperature. In a similar operation to the inversion-mode SOI MOSFETs in [1], the backgate was used to keep a sheet of mobile charges on the flake back-side by its quasi-flatband operation at a fixed voltage (0 V). Afterward, the top-gate was used as the active gate to perform mobile charge accumulation or depletion in the channel. Fig. 1 shows the device architecture together with the high frequency R-C equivalent circuit model for this underlap gate architecture. Fig. 2 represents the top-view microscope picture of the fabricated MoS₂ bulk MOSFET with a flake thickness of 38 nm, measured by AFM. The fabrication steps include mechanical exfoliation of MoS₂ crystals on a 260 nm thick oxidized Si substrate, e-beam lithography to make S/D pads, 50 nm Ni by thermal evaporation and lift-off, gate patterning, high-k/metal-gate stack deposition (1 nm of SiO_x by thermal evaporation, 11 nm of ZrO₂ by ALD deposition at 105 °C, 30 nm of Ni by thermal evaporation) and lift-off. The measurements were done at room temperature using an Agilent B1500A Semiconductor Parameter Analyzer. Fig. 3 shows its I_d-V_g, reporting a subthreshold slope of 110 mV/dec. and I_on/I_off of ∼1×10⁵, both at V_ds=100 mV.</p>

Topics

• Deposition
• impedance spectroscopy
• mobility
• atomic force microscopy
• dielectric constant
• semiconductor
• evaporation
• lithography