• Ruiz Euler, Hans-Christian
• Broersma, Hajo
• Van De Ven, Bram
• Bobbert, Peter A.
• Ibarra, Unai Alegre

Abstract

The rapidly growing computational demands of deep neural networks require novel hardware designs. Recently, tuneable nanoelectronic devices were developed based on hopping electrons through a network of dopant atoms in silicon. These ‘dopant network processing units’ (DNPUs) are highly energy-efficient and have potentially very high throughput. By adapting the control<br/>voltages applied to its electrodes, a single DNPU can solve a variety of linearly non-separable classification problems. However, using a single device has limitations due to the implicit single-node architecture. This paper presents a promising novel approach to neural information processing by introducing DNPUs as high-capacity neurons and moving from a single to a multi-neuron framework. By implementing and testing a small multi-DNPU classifier in hardware, we show that feed-forward DNPU networks improve the performance of a single DNPU from 77% to 94% test accuracy on a binary classification task with concentric classes on a plane. Furthermore, motivated by the integration of DNPUs with memristor crossbar arrays, we study the potential of using DNPUs in combination with linear layers. We show by simulation that an MNIST classifierwith only 10 DNPU nodes achieves over 96% test accuracy. Our results pave the road towards hardware neural network emulators that offer atomic-scale information processing with low latency and energy consumption.

Topics

• simulation
• Silicon