Materials Map

Discover the materials research landscape. Find experts, partners, networks.

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The Materials Map is an open tool for improving networking and interdisciplinary exchange within materials research. It enables cross-database search for cooperation and network partners and discovering of the research landscape.

The dashboard provides detailed information about the selected scientist, e.g. publications. The dashboard can be filtered and shows the relationship to co-authors in different diagrams. In addition, a link is provided to find contact information.

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Materials Map under construction

The Materials Map is still under development. In its current state, it is only based on one single data source and, thus, incomplete and contains duplicates. We are working on incorporating new open data sources like ORCID to improve the quality and the timeliness of our data. We will update Materials Map as soon as possible and kindly ask for your patience.

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in Cooperation with on an Cooperation-Score of 37%

Topics

Publications (3/3 displayed)

  • 2019Hexagonal germanium formation at room temperature using controlled penetration depth nano-indentation29citations
  • 2018Passivation of Ge/high-κ interface using RF Plasma nitridation8citations
  • 2017Germanium MOS capacitors grown on Silicon using low temperature RF-PECVD8citations

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Dushaq, Ghada
3 / 7 shared
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2019
2018
2017

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  • Dushaq, Ghada
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article

Germanium MOS capacitors grown on Silicon using low temperature RF-PECVD

  • Nayfeh, Ammar
  • Dushaq, Ghada
Abstract

<p>In this paper, Ge metal-oxide-semiconductor capacitors (MOSCAPs) are fabricated on Si using a low temperature two-step deposition technique by radio frequency plasma enhanced chemical vapor deposition. The MOSCAP gate stack consists of atomic layer deposition of Al<sub>2</sub>O<sub>3</sub> as the gate oxide and a Ti/Al metal gate electrode. The electrical characteristics of 9 nm Al<sub>2</sub>O<sub>3</sub>/i-Ge/Si MOSCAPs exhibit an n-type (p-channel) behavior and normal high frequency C-V responses. In addition to CV measurements, the gate leakage versus the applied voltage is measured and discussed. Moreover, the electrical behavior is discussed in terms of the material and interface quality. The Ge/high-k interface trap density versus the surface potential is extracted using the most commonly used methods in detemining the interface traps based on the capacitance-voltage (C-V) curves. The discussion included the Dit calculation from the conductance method, the high-low frequency (Castagné-Vapaille) method, and the Terman (high-frequency) method. Furthermore, the origins of the discrepancies in the interface trap densities determined from the different methods are discussed. The study of the post annealed Ge layers at different temperatures in H<sub>2</sub> and N<sub>2</sub> gas ambient revealed an improved electrical and transport properties of the films treated at T &lt; 600 °C. Also, samples annealed at &lt;550 °C show the lowest threading dislocation density of ∼1 × 10<sup>6</sup> cm<sup>-2</sup>. The low temperature processing of Ge/Si demonstrates a great potential for p-channel transistor applications in a monolithically integrated CMOS platform.</p>

Topics
  • density
  • impedance spectroscopy
  • surface
  • semiconductor
  • dislocation
  • Silicon
  • chemical vapor deposition
  • atomic layer deposition
  • Germanium