People | Locations | Statistics |
---|---|---|
Naji, M. |
| |
Motta, Antonella |
| |
Aletan, Dirar |
| |
Mohamed, Tarek |
| |
Ertürk, Emre |
| |
Taccardi, Nicola |
| |
Kononenko, Denys |
| |
Petrov, R. H. | Madrid |
|
Alshaaer, Mazen | Brussels |
|
Bih, L. |
| |
Casati, R. |
| |
Muller, Hermance |
| |
Kočí, Jan | Prague |
|
Šuljagić, Marija |
| |
Kalteremidou, Kalliopi-Artemi | Brussels |
|
Azam, Siraj |
| |
Ospanova, Alyiya |
| |
Blanpain, Bart |
| |
Ali, M. A. |
| |
Popa, V. |
| |
Rančić, M. |
| |
Ollier, Nadège |
| |
Azevedo, Nuno Monteiro |
| |
Landes, Michael |
| |
Rignanese, Gian-Marco |
|
Nayfeh, Ammar
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (3/3 displayed)
Places of action
Organizations | Location | People |
---|
article
Germanium MOS capacitors grown on Silicon using low temperature RF-PECVD
Abstract
<p>In this paper, Ge metal-oxide-semiconductor capacitors (MOSCAPs) are fabricated on Si using a low temperature two-step deposition technique by radio frequency plasma enhanced chemical vapor deposition. The MOSCAP gate stack consists of atomic layer deposition of Al<sub>2</sub>O<sub>3</sub> as the gate oxide and a Ti/Al metal gate electrode. The electrical characteristics of 9 nm Al<sub>2</sub>O<sub>3</sub>/i-Ge/Si MOSCAPs exhibit an n-type (p-channel) behavior and normal high frequency C-V responses. In addition to CV measurements, the gate leakage versus the applied voltage is measured and discussed. Moreover, the electrical behavior is discussed in terms of the material and interface quality. The Ge/high-k interface trap density versus the surface potential is extracted using the most commonly used methods in detemining the interface traps based on the capacitance-voltage (C-V) curves. The discussion included the Dit calculation from the conductance method, the high-low frequency (Castagné-Vapaille) method, and the Terman (high-frequency) method. Furthermore, the origins of the discrepancies in the interface trap densities determined from the different methods are discussed. The study of the post annealed Ge layers at different temperatures in H<sub>2</sub> and N<sub>2</sub> gas ambient revealed an improved electrical and transport properties of the films treated at T < 600 °C. Also, samples annealed at <550 °C show the lowest threading dislocation density of ∼1 × 10<sup>6</sup> cm<sup>-2</sup>. The low temperature processing of Ge/Si demonstrates a great potential for p-channel transistor applications in a monolithically integrated CMOS platform.</p>