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Naji, M. |
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Motta, Antonella |
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Aletan, Dirar |
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Mohamed, Tarek |
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Ertürk, Emre |
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Taccardi, Nicola |
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Kononenko, Denys |
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Petrov, R. H. | Madrid |
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Alshaaer, Mazen | Brussels |
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Bih, L. |
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Casati, R. |
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Muller, Hermance |
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Kočí, Jan | Prague |
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Šuljagić, Marija |
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Kalteremidou, Kalliopi-Artemi | Brussels |
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Azam, Siraj |
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Ospanova, Alyiya |
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Blanpain, Bart |
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Ali, M. A. |
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Popa, V. |
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Rančić, M. |
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Ollier, Nadège |
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Azevedo, Nuno Monteiro |
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Landes, Michael |
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Rignanese, Gian-Marco |
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Yngman, Sofie
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Publications (5/5 displayed)
- 2020Atomic Layer Deposition of Hafnium Oxide on InAs : Insight from Time-Resolved in Situ Studiescitations
- 2020Atomic Layer Deposition of Hafnium Oxide on InAscitations
- 2019GaN nanowires as probes for high resolution atomic force and scanning tunneling microscopycitations
- 2018InAs-oxide interface composition and stability upon thermal oxidation and high-k atomic layer depositioncitations
- 2015Structural Properties of Wurtzite InP-InGaAs Nanowire Core-Shell Heterostructurescitations
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article
InAs-oxide interface composition and stability upon thermal oxidation and high-k atomic layer deposition
Abstract
<p>Defects at the interface between InAs and a native or high permittivity oxide layer are one of the main challenges for realizing III-V semiconductor based metal oxide semiconductor structures with superior device performance. Here we passivate the InAs(100) substrate by removing the native oxide via annealing in ultra-high vacuum (UHV) under a flux of atomic hydrogen and growing a stoichiometry controlled oxide (thermal oxide) in UHV, prior to atomic layer deposition (ALD) of an Al<sub>2</sub>O<sub>3</sub> high-k layer. The semiconductor-oxide interfacial stoichiometry and surface morphology are investigated by synchrotron based X-ray photoemission spectroscopy, scanning tunneling microscopy, and low energy electron diffraction. After thermal oxide growth, we find a thin non-crystalline layer with a flat surface structure. Importantly, the InAs-oxide interface shows a significantly decreased amount of In<sup>3+</sup>, As<sup>5+</sup>, and As<sup>0</sup> components, which can be correlated to electrically detrimental defects. Capacitance-voltage measurements confirm a decrease of the interface trap density in gate stacks including the thermal oxide as compared to reference samples. This makes the concept of a thermal oxide layer prior to ALD promising for improving device performance if this thermal oxide layer can be stabilized upon exposure to ambient air.</p>