People | Locations | Statistics |
---|---|---|
Naji, M. |
| |
Motta, Antonella |
| |
Aletan, Dirar |
| |
Mohamed, Tarek |
| |
Ertürk, Emre |
| |
Taccardi, Nicola |
| |
Kononenko, Denys |
| |
Petrov, R. H. | Madrid |
|
Alshaaer, Mazen | Brussels |
|
Bih, L. |
| |
Casati, R. |
| |
Muller, Hermance |
| |
Kočí, Jan | Prague |
|
Šuljagić, Marija |
| |
Kalteremidou, Kalliopi-Artemi | Brussels |
|
Azam, Siraj |
| |
Ospanova, Alyiya |
| |
Blanpain, Bart |
| |
Ali, M. A. |
| |
Popa, V. |
| |
Rančić, M. |
| |
Ollier, Nadège |
| |
Azevedo, Nuno Monteiro |
| |
Landes, Michael |
| |
Rignanese, Gian-Marco |
|
Lind, Erik
Lund University
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (23/23 displayed)
- 2023Low temperature atomic hydrogen annealing of InGaAs MOSFETscitations
- 2023Time evolution of surface species during the ALD of high-k oxide on InAscitations
- 2023Time evolution of surface species during the ALD of high-k oxide on InAscitations
- 2023Tuning of Quasi-Vertical GaN FinFETs Fabricated on SiC Substratescitations
- 2023Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungstencitations
- 2022Oxygen relocation during HfO2 ALD on InAscitations
- 2022Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance.
- 2022Template-Assisted Selective Epitaxy of InAs on W
- 2021Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performancecitations
- 2020Atomic Layer Deposition of Hafnium Oxide on InAs : Insight from Time-Resolved in Situ Studiescitations
- 2020Atomic Layer Deposition of Hafnium Oxide on InAscitations
- 2016ZrO2 and HfO2 dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatmentcitations
- 2016ZrO2 and HfO2 dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatmentcitations
- 2014InAs nanowire MOSFETs in three-transistor configurations: single balanced RF down-conversion mixers.citations
- 2014Thin electron beam defined hydrogen silsesquioxane spacers for vertical nanowire transistorscitations
- 2013Interface characterization of metal-HfO2-InAs gate stacks using hard x-ray photoemission spectroscopy
- 2013Combining axial and radial nanowire heterostructures: Radial Esaki diodes and tunnel field-effect transistorscitations
- 2012Al2O3/InAs metal-oxide-semiconductor capacitors on (100) and (111)B substratescitations
- 2012High-Frequency Performance of Self-Aligned Gate-Last Surface Channel In0.53Ga0.47As MOSFETcitations
- 2011High Transconductance Self-Aligned Gate-Last Surface Channel In0.53Ga0.47As MOSFET
- 2011Interface composition of atomic layer deposited HfO2 and Al2O3 thin films on InAs studied by X-ray photoemission spectroscopycitations
- 2004Resonant tunneling permeable base transistor based pulsed oscillator
- 2004Tunneling Based Electronic Devices
Places of action
Organizations | Location | People |
---|
article
Combining axial and radial nanowire heterostructures: Radial Esaki diodes and tunnel field-effect transistors
Abstract
The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit. The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties. In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects, however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm2, than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm2 while their axial counterparts at most carry Jpeak = 77 kA/cm2, normalized to the largest cross-sectional area of the nanowire.