| People | Locations | Statistics |
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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Kononenko, Denys |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Kreupl, Franz
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (21/21 displayed)
- 2020Patterning Platinum by Selective Wet Etching of Sacrificial Pt-A1 Alloycitations
- 2019Graphenic carbon as etching mask: patterning with laser lithography and KOH etching
- 2019Highly Reliable Contacts to Silicon Enabled by Low Temperature Sputtered Graphenic Carbon
- 2018Carbon Wonderland from an Engineering Perspective
- 2017Graphenic Carbon: A Novel Material to Improve the Reliability of Metal-Silicon Contactscitations
- 2016Graphenic Carbon-Silicon Contacts for Reliability Improvement of Metal-Silicon Junctions
- 2016Graphenic carbon-silicon contacts for reliability improvement of metal-silicon junctionscitations
- 2015Trap passivation in memory cell with metal oxide switching element
- 2013TRAP PASSIVATION IN MEMORY CELL WITH METAL OXIDE SWITCHING ELEMENT
- 2013Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications—Part I: Process Developmentcitations
- 2012Integrated circuit including doped semiconductor line having conductive cladding
- 2011Integrated circuit including doped semiconductor line having conductive cladding
- 2010INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING
- 2009Integrated circuit including doped semiconductor line having conductive cladding
- 2007Silicon to nickel‐silicide axial nanowire heterostructures for high performance electronicscitations
- 2004High-current nanotube transistorscitations
- 2004Catalytic CVD of SWCNTs at Low Temperatures and SWCNT Devices
- 2004Chemical Vapor Deposition Growth of Single-Walled Carbon Nanotubes at 600 °C and a Simple Growth Modelcitations
- 2003Contact improvement of carbon nanotubes via electroless nickel depositioncitations
- 2001Method for fabricating an integrated circuit having at least one metallization plane
- 2001Template grown multiwall carbon nanotubes
Places of action
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article
Silicon to nickel‐silicide axial nanowire heterostructures for high performance electronics
Abstract
Silicon to nickel disilicide axial nanowire (NW) heterostructures have been fabricated and investigated extensively. To this end, intrinsic Si-NWs were grown by chemical vapor deposition using Au as the catalyst. The Si-NWs were contacted with Ni reservoirs so that upon annealing Ni diffused axially into the NWs. Single-crystalline NiSi 2 NW segments were formed at the diffusion path of Ni as proven by high-resolution transmission electron microscopy images. Further, the axial NiSi 2 to Si interfaces showed a sharpness of a couple of nanometers. Fully silicided NiSi 2 -NWs had maximal resistivities of 98 μΩ cm and conducted current densities of up to 205 MA/cm 2 before breakdown. Controlled silicidation from both NW ends gave NiSi 2 /Si/NiSi 2 axial NW heterostructures, which were implemented to fabricate Schottky contact field effect transistors (FET). The n ++ -substrate was used as a common back gate and the Si to NiSi 2 interfaces formed the Schottky source- and drain-(S/D) contacts to the active region. These Si-NW SB-FETs exhibited p-type behavior, and current densities in the on state of up to 0.8 MA/cm 2 for 1 V bias, the drain current could be modulated over a range of 10 7 . Moreover, the use of thin gate dielectrics enabled inverse subthreshold slopes as low as 110 mV/dec. These data show an efficient gate control over the devices by only using a back gate, due to an enhanced gate field coupling to the tip-like S/D-Schottky contacts.