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| Naji, M. |
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| Motta, Antonella |
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| Aletan, Dirar |
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| Mohamed, Tarek |
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| Ertürk, Emre |
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| Taccardi, Nicola |
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| Kononenko, Denys |
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| Petrov, R. H. | Madrid |
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| Alshaaer, Mazen | Brussels |
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| Bih, L. |
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| Casati, R. |
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| Muller, Hermance |
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| Kočí, Jan | Prague |
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| Šuljagić, Marija |
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| Kalteremidou, Kalliopi-Artemi | Brussels |
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| Azam, Siraj |
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| Ospanova, Alyiya |
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| Blanpain, Bart |
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| Ali, M. A. |
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| Popa, V. |
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| Rančić, M. |
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| Ollier, Nadège |
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| Azevedo, Nuno Monteiro |
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| Landes, Michael |
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| Rignanese, Gian-Marco |
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Liu, Chen
Imperial College London
in Cooperation with on an Cooperation-Score of 37%
Topics
Publications (9/9 displayed)
- 2024Contact‐Engineering of Self‐Aligned‐Gate Metal Oxide Transistors Processed via Electrode Self‐Delamination and Rapid Photonic Curingcitations
- 2021Influence of the base material on the mechanical behaviors of polycrystal-like meta-crystalscitations
- 2021Growth as an Alternative Approach to the Construction of Extra-Terrestrial Habitats
- 2021Growth as an Alternative Approach to the Construction of Extra-Terrestrial Habitats
- 2020Using soft polymer template engineering of mesoporous TiO2 scaffolds to increase perovskite grain size and solar cell efficiencycitations
- 2019Darcy’s Law for Yield Stress Fluidscitations
- 2010Optimisation of the properties of siloxane coatings as anti-biofouling coatings:Comparison of PACVD and hybrid PACVD-PVD coatingscitations
- 2009The potential of nano-structured silicon oxide type coatings deposited by PACVD for control of aquatic biofoulingcitations
- 2009Deposition parameters to improve the fouling-release properties of thin siloxane coatings prepared by PACVDcitations
Places of action
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article
Contact‐Engineering of Self‐Aligned‐Gate Metal Oxide Transistors Processed via Electrode Self‐Delamination and Rapid Photonic Curing
Abstract
<jats:title>Abstract</jats:title><jats:p>Metal oxide thin‐film transistors (TFTs) offer remarkable opportunities for applications in emerging transparent and flexible microelectronics. Unfortunately, their performance is hindered by limitations associated with parasitic effects, such as parasitic electrode overlap capacitances and high contact resistance, which can severely limit their dynamic behavior. Here, an innovative method is reported to fabricate coplanar self‐aligned‐gate (SAG) indium‐gallium‐zinc‐oxide (IGZO) transistors with engineered source/drain contacts. The manufacturing process starts with the deposition and patterning of a gate electrode/dielectric stack and its functionalization with an organic self‐assembled monolayer (SAM) as the surface energy modifier. A second gold (Au) electrode is subsequently deposited over the gate electrode stack. The overlapping region between the two electrodes is removed via self‐delamination under mild sonication, forming perfectly aligned coplanar Au‐Gate‐Au electrodes. Device fabrication is completed with the spin coating of the IGZO precursor, followed by rapid photonic curing. Replacing the gold source/drain contact with bimetallic electrodes such as Au/In and Au/ITO enables a reduction in contact resistance and improves the transistor performance remarkably without increasing manufacturing complexity. The method is highly scalable, robust, and applicable to other semiconductor materials.</jats:p>