• Saint-Patrice, Damien
• Munoz, Maria-Luisa Calvo
• Bernabe, Stéphane
• Velard, Rémi
• Pellerin, Thierry
• Virot, Leopold
• Deschaseaux, Edouard
• Charbonnier, Jean
• Thonnart, Yvain
• Assous, Myriam
• Hassan, Karim
• Malhouitre, Stephane

Abstract

This paper presents the integration of a photonic interposer designed to host 4 chiplets (28nm FDSOI) each integrating 16 cores and 6 RX/TX routers (28nm FDSOI) 3D stacked for many-core systems. Exascale computer has been one of the main driver in the field of HPC and Datacom and has recently been reached mainly thanks to co-design approach. The next breakthrough in HPC integration will probably come through photonic technology andoptical network-on-chip (ONoC) to overpass the bandwidth and the latency limitations ofelectrical links [1].This paper will detail the integration and the fabrication on the 200mm Leti platform of a Si photonic interposer on SOI wafers featuring Si 310nm on 800nm thick buried oxide (BOX). The photonic circuit operating at 1310nm wavelength is composed of silicon passive structures (Rib waveguides, SPGC, …) and actives devices (SiGeSi photodiodes, PIN ring modulators). TiN heaters embedded in SiO2 above the ring modulators allow tuning wavelength resonance of the device. Active devices and heaters are connected to the BEOL using W contacts.The TSV middle process (12x100µm) is detailed with the implementation of SiN sacrificial layer above photonic FEOL to protect W plugs. The 4 metals layers back-end process with 2 layers optimized for RF signals is also introduced as well as micropillars (Fig 1 - right). The backside processing is then explained with the interposer thinning at 100µm and a thermal cavity etching above the heaters The propagation losses are measured on RIB and DRIB structures and the insertion losses on SPGC structures both at the end of the FEOL and the BEOL process. The impact of the thermal back-end processes is then discussed. The TSV mid resistance have been evaluated with Kelvin test structure and daisy chains. The resistance is evaluated <22 mΩ with a yield > 95 % with the nominal diameter of 12µm. The dispersion of resistance values with the TSV diameter is also studied in the range of ± 1µm. The BEOL metal layers are characterized with DC test structures after each metal layer to evaluate the metal sheet resistance, the via resistance, the yield and the leakage current. The evolution of the metal and via performances within the processes is studied. Lock-in thermography analysis is performed on daisy chains and completed with Focused ion beam (FIB) cross-sections. The study has qualified all individual integration blocks required for the functional ONoC system developed currently in our group.

Topics

• impedance spectroscopy
• dispersion
• focused ion beam
• Silicon
• etching
• tin
• thermography