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Kanopoulos, Nick
in Cooperation with on an Cooperation-Score of 37%
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- 2018FABRICATION OF ELECTROCHROMIC PANES WITH GEL ELECTROLYTES AND NANOCOMPOSITE OXIDES FORMED WITH INKJET PRINTING
- 2014Scalable production of dye-sensitized solar cells using inkjet printing.
- 2002TESPAD: a testability specifications advisor for a structured test methodology
- 2002Design and implementation of a high-performance, modular, sorting engine
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Design and implementation of a high-performance, modular, sorting engine
Abstract
Abstract: This paper presents the design and implementation of a modular, expandable and high-performance sorter based on the rebound sorting algorithm. This single chip rebound sorter can sort 24, 32-bit or 64-bit records of 2's complement or unsigned data in either ascending or descending order. The modular design of the sorter allows direct cascading of chips for sorting more than 24 records. The monolithic sorter is implemented in 2.0 /spl mu/m CMOS technology, in a frame of 7.9 mm/spl times/9.2 mm, which supports its 84 I/O. A pipelining scheme was used to achieve a sustained throughput (of cascaded sorting chips) of 10 MHz, while a scan-path was used to allow external control of memory elements for testing purposes. The design of the sorter reported in this paper is a significant improvement in terms of functionality, versatility and performance, over previously reported monolithic sorter circuits.< > Published in: Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC